Simulation and characterization of a front-end ASIC for gaseous muon detectors
Petrow, Henri (2021-06-09)
Väitöskirja
09.06.2021
Lappeenranta-Lahti University of Technology LUT
Acta Universitatis Lappeenrantaensis
School of Engineering Science
School of Engineering Science, Laskennallinen tekniikka
Kaikki oikeudet pidätetään.
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In reference to IEEE copyrighted material which is used with permission in this thesis, the IEEE does not endorse any of Lappeenranta-Lahti University of Technology LUT's products or services. Internal or personal use of this material is permitted. If interested in reprinting/republishing IEEE copyrighted material for advertising or promotional purposes or for creating new collective works for resale or redistribution, please go to http://www.ieee.org/publications_ standards/publications/rights/rights_link.html to learn how to obtain a License from RightsLink.
Julkaisun pysyvä osoite on
https://urn.fi/URN:ISBN:978-952-335-673-3
https://urn.fi/URN:ISBN:978-952-335-673-3
Tiivistelmä
The Large hadron collider at CERN will get a luminosity upgrade in 2027. To cope with the increased particle rates, the compact muon solenoid (CMS) experiment will be upgraded with new gaseous muon detectors known as GEMs. These GEMs are large area, high density detectors which will face a high particle rate. A new-front end ASIC needed to be designed for them. The chip is known as VFAT3 and it is a crucial part of the new detector, converting the analog signal from the detector into a processable digital data. In this thesis, we study the operation and properties of the VFAT3 chip.
Mixed signal simulation methods were used during the design of the chip. With these methods the digital and analog parts of the chip could be designed alongside each other. This allowed the chip to be simulated as a whole throughout the design phase, which reduces the possibility of interface problems between different design blocks. The full chip simulation model was used to study the operation and usability of the chip and it allowed the co-development of the chip design and the physical verification platform.
A dedicated verification platform was designed for the full verification and characterization of the VFAT3. The platform is based around a Kintex-7 FPGA development kit, which is controlled by software running on a PC. The chip is connected to the kit with a series of custom-designed printed circuit boards, which provide the chip with powering and communication lines.
The results of the simulation, physical verification and characterization of the VFAT3 are presented and discussed.
The VFAT3 chip was found to be a reasonable solution for the use in the large area GEM readout. The chip showed good performance under the requirements set by the higher particle rate.
Mixed signal simulation methods were used during the design of the chip. With these methods the digital and analog parts of the chip could be designed alongside each other. This allowed the chip to be simulated as a whole throughout the design phase, which reduces the possibility of interface problems between different design blocks. The full chip simulation model was used to study the operation and usability of the chip and it allowed the co-development of the chip design and the physical verification platform.
A dedicated verification platform was designed for the full verification and characterization of the VFAT3. The platform is based around a Kintex-7 FPGA development kit, which is controlled by software running on a PC. The chip is connected to the kit with a series of custom-designed printed circuit boards, which provide the chip with powering and communication lines.
The results of the simulation, physical verification and characterization of the VFAT3 are presented and discussed.
The VFAT3 chip was found to be a reasonable solution for the use in the large area GEM readout. The chip showed good performance under the requirements set by the higher particle rate.
Kokoelmat
- Väitöskirjat [1029]